Gate stack resistance and limits to CMOS logic performance
- Richard A. Wachnik
- Sungjae Lee
- et al.
- 2014
- IEEE TCAS-I
Paper
Publications
6 results for Li-Hong Pan
Gate stack resistance and limits to CMOS logic performance
- Richard A. Wachnik
- S. Lee
- et al.
- 2013
- CICC 2013
Conference paperNovel high-performance analog devices for advanced low-power high-k metal gate complementary metal-oxide-semiconductor technology
- Jin-Ping Han
- Takashi Shimizu
- et al.
- 2011
- Japanese Journal of Applied Physics
PaperTransistor mismatch properties in deep-submicrometer CMOS technologies
- Xiaobin Yuan
- Takashi Shimizu
- et al.
- 2011
- IEEE T-ED
PaperRF modeling of 45nm low-power CMOS technology
- Jing Wang
- Hongmei Li
- et al.
- 2009
- NSTI-Nanotech 2009
Conference paperRF characterization and parameter extraction for CMOS device models
- John J. Pekarik
- Basanth Jagannathan
- et al.
- 2007
- SiRF 2007
Conference paper