Top level bus estimation for hierarchical design
- Ou He
- Suoming Pu
- et al.
- 2014
- ECS Transactions
Paper
Publications
4 results for Suoming Pu
Chip implementation on high-speed packet buffers in network system
- Suo Ming Pu
- Xia Li
- 2013
- ISOCC 2013
Conference paperRedesign modern IP router chips in a 3D technology
- Bo Yu
- Suoming Pu
- 2012
- APCCAS 2012
Conference paperRobustness and performance analysis on high speed ASIC design with canonical statistical timing model
- Suoming Pu
- Bo Yu
- et al.
- 2011
- ASICON 2011
Conference paper