Strained-silicon / silicon-germanium-on-insulator for high-performance CMOS : A manufacturable process for 300 mm substrates
- A. Reznicek
- S.W. Bedell
- et al.
- 2004
- ECS Meeting 2004
Conference paper
Publications
188 results for Devendra Sadana
A hydrogen pre-bake process for Si epitaxy on sige surface
- H. Chen
- S.W. Bedell
- et al.
- 2004
- ECS Meeting 2004
Conference paperObservation of stacking faults in strained Si layers
- S.W. Bedell
- K.E. Fogel
- et al.
- 2004
- Applied Physics Letters
PaperQualification of 300 mm SOI CMOS substrate material: Readiness for development and manufacturing
- H.J. Hovel
- M. Almonte
- et al.
- 2004
- Solid-State Electronics
PaperQuick turnaround technique for highlighting defects in thin Si/SiGe bilayers
- S.W. Bedell
- D.K. Sadana
- et al.
- 2004
- Electrochemical and Solid-State Letters
PaperA survey of defects in strained Si layers
- S.W. Bedell
- H. Chen
- et al.
- 2004
- MRS Proceedings 2004
Conference paperPerformance enhancement on sub-70 nm strained silicon SOI MOSFETS on ultra-thin thermally mixed strained silicon/SiGe on insulator(TM-SGOI) substrate with raised S/D
- B.H. Lee
- A.C. Mocuta
- et al.
- 2002
- IEDM 2002
Conference paperA patterned SOI by masked anneal for system-on-chip applications
- G.M. Cohen
- D.K. Sadana
- 2001
- MRS Proceedings 2001
Conference paperHigh performance 0.18 μm SOI CMOS technology
- E. Leobandung
- E. Barth
- et al.
- 1999
- IEDM 1999
Conference paper0.22 μm CMOS-SOI technology with a Cu BEOL
- A. Ajmera
- J. Sleight
- et al.
- 1999
- VLSI Technology 1999
Conference paper