Publications

4 results for F.D. Tamweber

Chip-level power-performance optimization through thermally-driven across-chip variation (ACV) reduction
- - X. Yu
  - Oleg Gluschenkov
  - et al.
- 2011
- IEDM 2011
Conference paper
Stress liner effects for 32-nm SOI MOSFETs with HKMG
- - Ming Cai
  - Karthik Ramani
  - et al.
- 2010
- IEEE T-ED
Paper
High performance 32nm SOI CMOS with high-k/metal gate and 0.149μm ² SRAM and ultra low-k back end with eleven levels of copper
- - B. Greene
  - Q. Liang
  - et al.
- 2009
- VLSI Technology 2009
Conference paper
Extending dual stress liner process to high performance 32nm node SOI CMOS manufacturing
- - M. Cai
  - B. Greene
  - et al.
- 2008
- IEEE International SOI Conference 2008
Conference paper