Publications

14 results for Brian L. Ji

Destructive-read Random Access Memory System Buffered with Destructive-read Memory Cache for SoC Applications
- - Brian L. Ji
  - Seiji Munetoh
  - et al.
- 2003
- VLSI Circuits 2003
Conference paper
A 7F² cell and bitline architecture featuring tilted array devices and penalty-free vertical BL twists for 4-Gb DRAM's
- - Heinz Hoenigschmid
  - Alexander Frey
  - et al.
- 2000
- IEEE Journal of Solid-State Circuits
Paper
A 220-mm², four- and eight-bank, 256-Mb SDRAM with single-sided stitched WL architecture
- - Toshiaki Kirihata
  - Martin Gall
  - et al.
- 1998
- IEEE Journal of Solid-State Circuits
Paper
220 mm² 4 and 8 bank 256 Mb SDRAM with single-sided stitched WL architecture
- - T. Kirihata
  - M. Gall
  - et al.
- 1998
- ISSCC 1998
Conference paper