FINFET technology featuring high mobility SiGe channel for 10nm and beyond
- Dechao Guo
- G. Karve
- et al.
- 2016
- VLSI Technology 2016
Conference paper
Publications
58 results for Terence B. Hook
Series resistance reduction in stacked nanowire FETs for 7-nm CMOS technology
- Anil K. Bansal
- Ishita Jain
- et al.
- 2016
- IEEE J-EDS
PaperEffects of trap-assisted tunneling on gate-induced drain leakage in silicon-germanium channel p-type FET for scaled supply voltages
- Vishal A. Tiwari
- Rama Divakaruni
- et al.
- 2016
- Japanese Journal of Applied Physics
PaperVertical Slit FET at 7-nm Node and beyond
- Ping-Lin Yang
- Terence B. Hook
- et al.
- 2016
- IEEE T-ED
PaperPerformance trade-offs in FinFET and gate-all-around device architectures for 7nm-node and beyond
- Seong-Dong Kim
- Michael Guillorn
- et al.
- 2015
- S3S 2015
Conference paperNanowire FET design for 7-nm SOI-CMOS technology
- Ishita Jain
- Anil K. Bansal
- et al.
- 2015
- S3S 2015
Conference paperScalability of planar FDSOI and FinFETs and What's in store for the future beyond that?
- Bruce Doris
- Terence B. Hook
- 2015
- ESSDERC 2015
Conference paperA novel ALD SiBCN low-k spacer for parasitic capacitance reduction in FinFETs
- Tenko Yamashita
- S. Mehta
- et al.
- 2015
- VLSI Technology 2015
Conference paperTransistor Matching and Fin Angle Variation in FinFET Technology
- Samarth Agarwal
- Terence B. Hook
- et al.
- 2015
- IEEE T-ED
PaperSuper fast physics-based methodology for accurate memory yield prediction
- Rajiv V. Joshi
- Keunwoo Kim
- et al.
- 2015
- IEEE Transactions on VLSI Systems
Paper