Advanced metallization developments for 32-nm node CMOS technology contact architecture
- Doug H. Lee
- Valli Arunachalam
- et al.
- 2009
- ADMETA 2009
Conference paper
Publications
4 results for Doug H. Lee
Stress liner effects for 32-nm SOI MOSFETs with HKMG
- Ming Cai
- Karthik Ramani
- et al.
- 2010
- IEEE T-ED
PaperHigh performance 32nm SOI CMOS with high-k/metal gate and 0.149μm 2 SRAM and ultra low-k back end with eleven levels of copper
- B. Greene
- Q. Liang
- et al.
- 2009
- VLSI Technology 2009
Conference paperExtending dual stress liner process to high performance 32nm node SOI CMOS manufacturing
- M. Cai
- B. Greene
- et al.
- 2008
- IEEE International SOI Conference 2008
Conference paper