A Cryo-CMOS Transmon Qubit Controller and Verification with FPGA Emulation
- Kevin Tien
- Ken Inoue
- et al.
- 2022
- DATE 2022
Conference paper
Publications
65 results for John F. Bulzacchelli
A Cryo-CMOS Low-Power Semi-Autonomous Qubit State Controller in 14nm FinFET Technology
- David J. Frank
- Sudipto Chakraborty
- et al.
- 2022
- ISSCC 2022
Conference paperDistributed Network of LDO Microregulators Providing Submicrosecond DVFS and IR Drop Compensation for a 24-Core Microprocessor in 14-nm SOI CMOS
- Miguel E. Perez
- Michael A. Sperling
- et al.
- 2020
- IEEE JSSC
PaperA 128-Gb/s 1.3-pJ/b PAM-4 Transmitter with Reconfigurable 3-Tap FFE in 14-nm CMOS
- Zeynep Toprak-Deniz
- Jonathan E. Proesel
- et al.
- 2020
- IEEE JSSC
PaperDistributed Network of LDO Microregulators Providing Submicrosecond DVFS and IR Drop Compensation for a 24-Core Microprocessor in 14nm SOI CMOS
- Miguel E. Perez
- Michael A. Sperling
- et al.
- 2019
- CICC 2019
Conference paper6.6 A 128Gb/s 1.3pJ/b PAM-4 Transmitter with Reconfigurable 3-Tap FFE in 14nm CMOS
- Zeynep Toprak-Deniz
- Jonathan E. Proesel
- et al.
- 2019
- ISSCC 2019
Conference paperA 32 Gb/s, 4.7 pJ/bit Optical Link With-11.7 dBm Sensitivity in 14-nm FinFET CMOS
- Jonathan E. Proesel
- Zeynep Toprak-Deniz
- et al.
- 2018
- IEEE JSSC
PaperA 32Gb/s, 4.7pJ/bit optical link with-11.7dBm sensitivity in 14nm FinFET CMOS
- Jonathan E. Proesel
- Zeynep Toprak-Deniz
- et al.
- 2017
- VLSI Circuits 2017
Conference paperA 28.05Gb/s transceiver using quarter-rate triple-speculation hybrid-DFE receiver with calibrated sampling phases in 32nm CMOS
- Gautam Gangasani
- John F. Bulzacchelli
- et al.
- 2017
- VLSI Circuits 2017
Conference paperA 1.8 pJ/bit 16 × 16Gb/s source-synchronous parallel interface in 32nm SOI CMOS with receiver redundancy for link recalibration
- Timothy O. Dickson
- Yong Liu
- et al.
- 2016
- IEEE JSSC
Paper