Process-variation-tolerant clock skew minimization
- Shen Lin
- C.K. Wong
- 1994
- IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Paper
Publications
114 results for C.K. Wong
Timing analysis algorithm for circuits with level-sensitive latches
- Jin-Fuw Lee
- D.T. Tang
- et al.
- 1994
- IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
PaperMinimizing via coupled noise in high performance thermal conduction module design
- Howard H. Chen
- C.K. Wong
- 1994
- APCCAS 1994
Conference paperOn Bends and Distances of Paths Among Obstacles in Two-Layer Interconnection Model
- D.T. Lee
- C.D. Yang
- et al.
- 1994
- IEEE TC
PaperA Weighted Steiner Tree-Based Global Router with Simultaneous Length and Density Minimization
- C. Chiang
- C.K. Wong
- et al.
- 1994
- IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
PaperProcess-variation-tolerant zero skew clock routing
- Shen Lin
- C.K. Wong
- 1993
- Annual ASIC Conference and Exhibit 1993
Conference paperWiring for manufacturability and yield maximization in computer-aided VLSI design
- Howard H. Chen
- C.K. Wong
- 1993
- VLSI-TSA 1993
Conference paperWiring and crosstalk avoidance in multi-chip module design
- Howard H. Chen
- C.K. Wong
- 1992
- CICC 1992
Conference paperAn algorithm for exact rectilinear Steiner trees for switchbox with obstacles
- Charles Chiang
- Majid Sarrafzadeh
- et al.
- 1992
- ISCAS 1992
Conference paperProvably good algorithms for performance-driven global routing
- J. Cong
- A. Kahng
- et al.
- 1992
- ISCAS 1992
Conference paper