Josephson 4 K-bit cache memory design for a prototype signal processor. II. Cell array and drivers
- W.H. Henkels
- L.M. Geppert
- et al.
- 1985
- Journal of Applied Physics
Paper
Publications
27 results for W.H. Henkels
Josephson 4 K-bit cache memory design for a prototype signal processor. III. Decoding, sensing, and timing
- W.H. Henkels
- L.M. Geppert
- et al.
- 1985
- Journal of Applied Physics
PaperAn experimental memory cell using edge-junction gates
- U. Deutsch
- T.V. Rajeevakumar
- et al.
- 1983
- IEEE Transactions on Magnetics
PaperExperimental Single Flux Quantum NDRO Josephson Memory Cell
- Walter H. Henkels
- James H. Greiner
- 1979
- IEEE JSSC
PaperAn Experimental 64-Bit Decoded Josephson NDRO Random Access Memory
- Walter H. Henkels
- Hans H. Zappe
- 1978
- IEEE JSSC
PaperPenetration depth measurements on type II superconducting films
- W.H. Henkels
- C.J. Kircher
- 1977
- IEEE Transactions on Magnetics
PaperAn elementary logic circuit employing superconducting josephson tunneling gates
- W.H. Henkels
- 1974
- IEEE Transactions on Magnetics
Paper