An Eight-Lane 7-Gb/s/pin Source Synchronous Single-Ended RX with Equalization and Far-End Crosstalk Cancellation for Backplane Channels
- Cosimo Aprile
- Alessandro Cevrero
- et al.
- 2018
- IEEE JSSC
Paper
Publications
121 results at IEEE JSSC
A 64-Gb/s 1.4-pJ/b NRZ Optical Receiver Data-Path in 14-nm CMOS FinFET
- Ilter Ozkaya
- Alessandro Cevrero
- et al.
- 2017
- IEEE JSSC
PaperA Wide Dynamic Range Buck Converter with Sub-nW Quiescent Power
- Arun Paidimarri
- Anantha P. Chandrakasan
- 2017
- IEEE JSSC
PaperA 28-GHz 32-Element TRX Phased-Array IC with Concurrent Dual-Polarized Operation and Orthogonal Phase and Gain Control for 5G Communications
- Bodhisatwa Sadhu
- Yahya Tousi
- et al.
- 2017
- IEEE JSSC
PaperA low voltage SRAM using resonant supply boosting
- Rajiv V. Joshi
- Matt Ziegler
- et al.
- 2017
- IEEE JSSC
PaperA Resistance Drift Compensation Scheme to Reduce MLC PCM Raw BER by Over 100× for Storage Class Memory Applications
- Win-San Khwa
- Meng-Fan Chang
- et al.
- 2017
- IEEE JSSC
PaperA Nonvolatile Flip-Flop-Enabled Cryptographic Wireless Authentication Tag With Per-Query Key Update and Power-Glitch Attack Countermeasures
- Hyung-Min Lee
- Chiraag S. Juvekar
- et al.
- 2017
- IEEE JSSC
PaperA 1.8 pJ/bit 16 × 16Gb/s source-synchronous parallel interface in 32nm SOI CMOS with receiver redundancy for link recalibration
- Timothy O. Dickson
- Yong Liu
- et al.
- 2016
- IEEE JSSC
PaperA Low Ripple Switched-Capacitor Voltage Regulator Using Flying Capacitance Dithering
- Suyoung Bang
- Jae-Sun Seo
- et al.
- 2016
- IEEE JSSC
PaperImplementation of Low-Power 6-8 b 30-90 GS/s Time-Interleaved ADCs With Optimized Input Bandwidth in 32 nm CMOS
- Lukas Kull
- J. Pliva
- et al.
- 2016
- IEEE JSSC
Paper