The smart grid and key research technical challenges
- Michael G. Rosenfield
- 2010
- VLSI Technology 2010
Conference paper
Publications
9 results at VLSI Technology 2010
Gate-all-around silicon nanowire 25-stage CMOS ring oscillators with diameter down to 3 nm
- Sarunya Bangsaruntip
- A. Majumdar
- et al.
- 2010
- VLSI Technology 2010
Conference paperIII-V: Replacing Si or more than moore?
- Yanning Sun
- 2010
- VLSI Technology 2010
Conference paperFDSOI CMOS with dielectrically-isolated back gates and 30nm LG high-κ/metal gate
- Marwan Khater
- J. Cai
- et al.
- 2010
- VLSI Technology 2010
Conference paperHighly scalable novel access device based on Mixed Ionic Electronic Conduction (MIEC) materials for high density phase change memory (PCM) arrays
- K. Gopalakrishnan
- R.S. Shenoy
- et al.
- 2010
- VLSI Technology 2010
Conference paperA 0.063 μm2 FinFET SRAM cell demonstration with conventional lithography using a novel integration scheme with aggressively scaled fin and gate pitch
- Veeraraghvan S. Basker
- Theodorus E. Standaert
- et al.
- 2010
- VLSI Technology 2010
Conference paperStudy of channel length scaling in large-scale graphene FETs
- Shu-Jen Han
- Yanning Sun
- et al.
- 2010
- VLSI Technology 2010
Conference paperDesign-technology interaction for post-32 nm node CMOS technologies
- Ghavam G. Shahidi
- 2010
- VLSI Technology 2010
Conference paperUltra-thin-body and BOX (UTBB) Fully Depleted (FD) device integration for 22nm node and beyond
- Q. Liu
- A. Yagishita
- et al.
- 2010
- VLSI Technology 2010
Conference paper