Optimal CMOS cell transistor placement: A relaxation approachAndre StaufferRavi Nair1987ICCAD 1987Conference paper
Improved logic optimization using global flow analysisLeonard BermanLouise Trevillyan1987ICCAD 1987Conference paper
On the design of robust multiple fault testable CMOS combinational logic circuitsSandip KunduSudhakar M. Reddyet al.1987ICCAD 1987Conference paper