Lane Meyer

Lane Meyer began his career in semiconductor manufacturing at GlobalFoundries Fab 8 in 2017 before graduating from Rensselaer Polytechnic Institute (RPI). Since 2018, Lane has been a mainstay on IBM’s Industrial Engineering (IE) team at Albany NanoTech.

In his role supporting Fab Operations, Lane has been involved in numerous programs onsite. Most notably was planning and tracking the world's first hardware demonstration of a chip with 2 nanometer technology in 2021. This feat in logic scaling called Nanosheets is being further developed through the Rapidus partnership.

Lane is an expert in creating detailed production schedules called waterfalls which require auditing the raw process time (RPT) for thousands of individual steps in the manufacturing flow, factoring in design of experiments, upcoming scheduled tool downtime, and collaborating with researchers on additional engineering efforts. For three years, Lane was the IE lead for Rocket Lots, the highest priority wafers with the fastest cycle time for expediting device verification milestones. Since 2025, this effort has transitioned to helping develop quantum hardware for Anderon.

Industrial Engineering is also delegated across tooling sectors. While Lane has covered most sectors onsite, his current concentrations are lithography (LTH), rapid thermal processing (RTP), selective dry etch (SDE), ion implantation (ION), and wafer bonding (BND). Sector responsibilities include capacity sizing, analyzing tool performance, alleviating pinch points, and driving continuous improvement projects.

Behind the scenes, Lane has maintained the site-wide Productivity Target Model which analyzes large amounts of tool utilization, customer usage, and production data to calculate daily productivity benchmarks. This was instrumental in defining the roadmap for increasing IBM productivity.