Matthias Brändli

Publications

• A 2-Lane Discrete Multitone Wireline Receiver Datapath With Far-End Crosstalk Cancellation on RFSoC Platform

  • • Jaewon Lee
    • Seoyoung Jang
    • et al.
  • 2024
  • IEEE TCAS-II

  Paper

• A Loop-Break Decision Feedback Equalizer for DAC/ADC-DSP-Based Wireline Transceivers

  • • Donggeon Kim
    • Yujin Choi
    • et al.
  • 2024
  • IEEE TCAS-I

  Paper

• A Discrete Multitone Wireline Transceiver Datapath With On-Chip Sign-Sign LMS Adaptation and Loading Profile Optimization on RFSoC

  • • Jaewon Lee
    • Seoyoung Jang
    • et al.
  • 2024
  • IEEE TCAS-II

  Paper

• A DAC/ADC-Based Wireline Transceiver Datapath Functional Verification on RFSoC Platform

  • • Jaewon Lee
    • Seoyoung Jang
    • et al.
  • 2024
  • IEEE TCAS-II

  Paper

• Design of synchronous frequency dividers in 5-nm FinFET CMOS technology

  • • Marcel Kossel
    • Pier Andrea Francese
    • et al.
  • 2023
  • Electronics Letters

  Paper

• Design of Time-Encoded Spiking Neural Networks in 7-nm CMOS Technology

  • • Sandro Widmer
    • Marcel Kossel
    • et al.
  • 2023
  • IEEE TCAS-II

  Paper

• A 64-core mixed-signal in-memory compute chip based on phase-change memory for deep neural network inference

  • • Manuel Le Gallo
    • Riduan Khaddam-Aljameh
    • et al.
  • 2023
  • Nature Electronics

  Paper

• A 72-GS/s, 8-Bit DAC-Based Wireline Transmitter in 4-nm FinFET CMOS for 200+ Gb/s Serial Links

  • • Timothy O. Dickson
    • Zeynep Toprak Deniz
    • et al.
  • 2023
  • IEEE JSSC

  Paper

• An 8b 1.0-to-1.25GS/s 0.7-to-0.8V Single-Stage Time-Based Gated-Ring-Oscillator ADC with 2× Interpolating Sense-Amplifier-Latches

  • • Abdullah Serdar Yonar
    • Pier Andrea Francese
    • et al.
  • 2023
  • ISSCC 2023

  Conference paper

• An 8b 1.0-to-1.25 GS/s Time-Based ADC With Bipolar VTC and Sense Amplifier Latch Interpolated Gated Ring Oscillator TDC

  • • A. Serdar Yonar
    • Pier Andrea Francese
    • et al.
  • 2023
  • IEEE SSC-L

  Paper