Matthias Brändli

Publications

• A 60 Gb/s 1.9 pJ/bit NRZ optical-receiver with low latency digital CDR in 14nm CMOS FinFET

  • • Alessandro Cevrero
    • Ilter Ozkaya
    • et al.
  • 2017
  • VLSI Circuits 2017

  Conference paper

• A 5Gb/s 7.1fJ/b/mm 8× multi-drop on-chip 10mm data link in 14nm FinFET CMOS SOI at 0.5V

  • • Elisa Sacco
    • Pier Andrea Francese
    • et al.
  • 2017
  • VLSI Circuits 2017

  Conference paper

• A 12b 61dB SNDR 300MS/s SAR ADC with inverter-based preamplifier and common-mode-regulation DAC in 14nm CMOS FinFET

  • • Danny Luu
    • Lukas Kull
    • et al.
  • 2017
  • VLSI Circuits 2017

  Conference paper

• A 10b 1.5GS/s pipelined-SAR ADC with background second-stage common-mode regulation and offset calibration in 14nm CMOS FinFET

  • • Lukas Kull
    • Danny Luu
    • et al.
  • 2017
  • ISSCC 2017

  Conference paper

• A 64Gb/s 1.4pJ/b NRZ optical-receiver data-path in 14nm CMOS FinFET

  • • Alessandro Cevrero
    • Ilter Ozkaya
    • et al.
  • 2017
  • ISSCC 2017

  Conference paper

• Modeling and Pareto Optimization of On-Chip Switched Capacitor Converters

  • • Toke M. Andersen
    • Florian Krismer
    • et al.
  • 2017
  • IEEE-TEPL

  Paper

• A 10 W On-Chip Switched Capacitor Voltage Regulator with Feedforward Regulation Capability for Granular Microprocessor Power Delivery

  • • Toke M. Andersen
    • Florian Krismer
    • et al.
  • 2017
  • IEEE-TEPL

  Paper

• CMOS ADCs Towards 100 GS/s and beyond

  • • Lukas Kull
    • Danny Luu
    • et al.
  • 2016
  • CSICS 2016

  Conference paper

• Feedback delay reduction of Tomlinson- Harashima precoder in 14 nm CMOS via pipelined MAC units operated entirely with CSA arithmetic

  • • Marcel Kossel
    • Matthias Braendli
    • et al.
  • 2016
  • Electronics Letters

  Paper

• A 4.1 pJ/b 25.6 Gb/s 4-PAM reduced-state sliding-block Viterbi detector in 14 nm CMOS

  • • Hazar Yueksel
    • Matthias Braendli
    • et al.
  • 2016
  • ESSCIRC 2016

  Conference paper