Very low voltage (VLV) design
- Ramon Bertran
- Pradip Bose
- et al.
- 2017
- ICCD 2017
Conference paper
Swagath Venkataramani
Title
Principal Research Scientist, AIU Architecture and Compilers
Publications
POSTER: Design Space Exploration for Performance Optimization of Deep Neural Networks on Shared Memory Accelerators
- Swagath Venkataramani
- Jungwook Choi
- et al.
- 2017
- PACT 2017
Conference paperScaledeep: A scalable compute architecture for learning and evaluating deep networks
- Swagath Venkataramani
- Ashish Ranjan
- et al.
- 2017
- ISCA 2017
Conference paperINVITED: Accelerator Design for Deep Learning Training: Extended Abstract: Invited
- Ankur Agrawal
- Chia-Yu Chen
- et al.
- 2017
- DAC 2017
Conference paper
Patents
- CN
- ZL202080055389.3
- DE
- 11 2020 004 067
- US
- 12468947
- US
- 12423567
- CN
- ZL202080065781.6
- US
- 12399743
- FR
- 4558932
- DE
- 602023005939.1
- GB
- 4558932
- KR
- 10-2843494
Top collaborators
AM
Alberto Mannari
Software Developer
PC
Prasanth Chatarasi
Staff Research Scientist, AIU Accelerator Compilers and Architecture
MZ
Matthew Ziegler
Principal Research Scientist
MK
Monodeep Kar
Staff Research Scientist