Geoffrey Burr, Sidney Tsai, et al.
CICC 2025
This brief presents a 1 mA–1050 mA computational DLDO for modern SoCs that achieves fast load transient, high efficiency, and fast DVS. A rising -edge computation enables accurate load prediction with only 1 nF Cout, while a load -dependent feedback maintains low ripple across a wide load range. Reusing the computation hardware for DVS improves the DVS rate by 4.6×. Fabricated in 28-nm CMOS, the DLDO achieves 0.15 ps FoM, 46.2 mV/ns DVS, <17 mV ripple, and 99.98% peak current efficiency.
Geoffrey Burr, Sidney Tsai, et al.
CICC 2025
Olivier Maher, N. Harnack, et al.
DRC 2023
Shubham Jain, Ritik Raj
PyTorch Conference 2026
Thomas Lesueur, David Danovitch, et al.
ECTC 2025