Conference paper
SOI lateral bipolar transistor with drive current >3mA/μm
J. Cai, Tak H. Ning, et al.
S3S 2013
A bulk silicon divide-by-two dynamic frequency divider with maximum clock speed of 26.5 GHz has been achieved. The dynamic divider operates from 6.5 GHz to 26.5 GHz. The design is based on n-channel MOSFET's with an effective gate length of 0.1 µm. © 2000, The Institute of Electrical and Electronics Engineers, Inc. All rights reserved.
J. Cai, Tak H. Ning, et al.
S3S 2013
Keith A. Jenkins
IEEE T-ED
Yu-Ming Lin, Alberto Valdes-Garcia, et al.
Science
Alberto Valdes-Garcia, Fengnian Xia, et al.
IMS 2013