A Cryo-CMOS Control System for Large-Scale Superconducting Qubit Quantum Computing: Part 1

Fault-tolerant quantum computing demands scalable innovation across all quantum system layers, particularly in control electronics, where size, power consumption, and deployment costs must be significantly reduced versus today’s solutions. We present the first large-scale demonstration of cryogenic CMOS (cryo-CMOS) control for superconducting qubit quantum systems within a hybrid architecture that combines cryogenic flux control ASICs with room-temperature RF electronics for qubit drive, readout, and state discrimination.

The system integrates multiple cryo-CMOS ASICs, each supporting 16 independently programmable flux channels comprised of a microcontroller and an associated high-precision DACs, enabling low-noise, low-power flux biasing optimized for high-fidelity two-qubit gates. The ASICs are housed in multi-chip packages, compatible with high-density flex ribbons, and thermally anchored to a dedicated cryo-cooler.

This hybrid control solution is deployed on IBM’s 156-qubit Heron R2 processor and characterized across a broad range of operating conditions—including thermal stability, signal integrity, and noise performance—demonstrating model-to-hardware alignment with system design targets. These results establish the viability of the hybrid architecture as a path to achieving required reduction in size, power consumption, and costs central to delivering fault-tolerant superconducting qubit-based quantum computing solutions.