Asymmetrical triple-gate FET
Meng-Hsueh Chiang, Jeng-Nan Lin, et al.
SISPAD 2007
This paper presents a new self-alignment concept for scaled-down bipolar transistors: the self-aligned lateral profile. Using this concept to form the impurity profile and combining it with a wraparound base contact to reduce the emitter-base contact spacing and an n+-polyrefractory metal emitter stack to reduce the emitter resistance, a highperformance and potentially high-yield device structure can be obtained. The device structure can be adapted to a CMOS or merged bipolar-CMOS process and can also be easily optimized for analog applications. Copyright © 1987 by The Institute of Electrical and Electronics Engineers, Inc.
Meng-Hsueh Chiang, Jeng-Nan Lin, et al.
SISPAD 2007
Keunwoo Kim, Ching-Te Chuang, et al.
VLSI-TSA 2003
Chunjian Ni, Rajiv V. Joshi, et al.
ASME Electronic and Photonics Packaging Division 2007
Ching-Te Chuang, Kerry Bernstein, et al.
IEEE Circuits and Devices Magazine