Shih-Hsien Lo, Koushik K. Das, et al.
VLSI-DAT 2007
This paper presents a new self-alignment concept for scaled-down bipolar transistors: the self-aligned lateral profile. Using this concept to form the impurity profile and combining it with a wraparound base contact to reduce the emitter-base contact spacing and an n+-polyrefractory metal emitter stack to reduce the emitter resistance, a highperformance and potentially high-yield device structure can be obtained. The device structure can be adapted to a CMOS or merged bipolar-CMOS process and can also be easily optimized for analog applications. Copyright © 1987 by The Institute of Electrical and Electronics Engineers, Inc.
Shih-Hsien Lo, Koushik K. Das, et al.
VLSI-DAT 2007
Keunwoo Kim, Rajiv V. Joshi, et al.
ISLPED 2003
G.P. Li, E. Hackbarth, et al.
IEEE T-ED
Satish Kumar, Rajiv V. Joshi, et al.
IEDM 2006