Sub-15 ps charge-buffered active-pull-down ECL/NTL circuits
Ken Chin, Ching-Te Chuang, et al.
CICC 1992
This paper presents a new self-alignment concept for scaled-down bipolar transistors: the self-aligned lateral profile. Using this concept to form the impurity profile and combining it with a wraparound base contact to reduce the emitter-base contact spacing and an n+-polyrefractory metal emitter stack to reduce the emitter resistance, a highperformance and potentially high-yield device structure can be obtained. The device structure can be adapted to a CMOS or merged bipolar-CMOS process and can also be easily optimized for analog applications. Copyright © 1987 by The Institute of Electrical and Electronics Engineers, Inc.
Ken Chin, Ching-Te Chuang, et al.
CICC 1992
Jente B. Kuang, David H. Allen, et al.
IEEE Journal of Solid-State Circuits
G.P. Li, C.T. Chuang, et al.
IEEE T-ED
Ching-Te Chuang, Denny D. Tang, et al.
IEEE Journal of Solid-State Circuits