Circuit techniques utilizing independent gate control in double-gate technologies
- Jente B. Kuang
- Keunwoo Kim
- et al.
- 2008
- IEEE Transactions on VLSI Systems
Paper
Publications
136 results for C.T. Chuang
Optimal design of triple-gate devices for high-performance and low-power applications
- Meng-Hsueh Chiang
- Jeng-Nan Lin
- et al.
- 2008
- IEEE Transactions on Electron Devices
PaperOptimal dual-VT design in sub-100 nanometer PDSOI and double-gate technologies
- Aditya Bansal
- Jae-Joon Kim
- et al.
- 2008
- VLSID 2008
Conference paperOptimal dual-VT design in sub-100-nm PD/SOI and double-gate technologies
- Aditya Bansal
- Jae-Joon Kim
- et al.
- 2008
- IEEE Transactions on Electron Devices
PaperReducing parasitic BJT effects in partially depleted SOI digital logic circuits
- Koushik K. Das
- Ching-Te Chuang
- et al.
- 2008
- Microelectronics Journal
PaperA floating-body dynamic supply boosting technique for low-voltage sram in nanoscale PD/SOI CMOS technologies
- Rajiv Joshi
- Rouwaida Kanj
- et al.
- 2007
- ISLPED 2007
Conference paperA high-performance, low leakage, and stable SRAM row-based back-gate biasing scheme in FinFET technology
- Rajiv V. Joshi
- Keunwoo Kim
- et al.
- 2007
- VLSID 2007
Conference paperAccurate modeling and analysis of currents in trapezoidal FinFET devices
- R.M. Rao
- A. Bansal
- et al.
- 2007
- SOI 2007
Conference paperPhonon Boltzmann transport based electro-thermal analysis of nano-scale asymmetrical double-gate finfet device
- Chunjian Ni
- Rajiv V. Joshi
- et al.
- 2007
- ASME Electronic and Photonics Packaging Division 2007
Conference paperLeakage analysis for FinFET devices using self-consistent electro-thermal modeling
- Satish Kumar
- Rajiv V. Joshi
- et al.
- 2007
- ICICDT 2007
Conference paper