Nikolaos Chrysos, Fredy Neeser, et al.
IEEE Micro
Paper
Design methodology for a large communication chip
Abstract
Smart chip is a large communication chip with standard-based communication interfaces, multiple clock domains, and mixed-signal components for line interfacing. This chip has been developed by focusing mainly on general design aspects.
Related
Conference paper
Arbitration of many thousand flows at 100G and beyond
Nikolaos Chrysos, Fredy Neeser, et al.
INA-OCMC 2013
Conference paper
A 22 Gbit/s PAM-4 receiver in 90nm CMOS-SOI technology
Thomas Toifl, Christian Menolfi, et al.
VLSI Circuits 2005
Rolf Clauberg, Armin Blacha
Journal of Applied Physics