Peter Vettiger, Gian-Luca Bona, et al.
IEEE JQE
Paper
Design methodology for a large communication chip
Abstract
Smart chip is a large communication chip with standard-based communication interfaces, multiple clock domains, and mixed-signal components for line interfacing. This chip has been developed by focusing mainly on general design aspects.
Related
Marcel Kossel, Thomas Morf, et al.
IEEE Journal of Solid-State Circuits
Marcel Kossel, Thomas Morf, et al.
IEEE MWCL
Martin L. Schmatz, Rik Jongerius, et al.
ICASSP 2014