Geoffrey Burr, Sidney Tsai, et al.
CICC 2025
For decades, Moore's Law has driven semiconductor progress through relentless transistor scaling (Fig. 1). However, as silicon devices reach atomic dimensions, physical and economic barriers - such as power density, interconnect limitations, and escalating fabrication costs - slow traditional scaling [1]. At the same time, as shown in Fig. 2, AI's rapid growth has exposed inefficiencies in conventional hardware, where memory access and data movement dominate power consumption, highlighting the need for new computing paradigms that minimize these bottlenecks [2]. To sustain innovation, the industry has shifted toward system-level scaling, where architectural advancements and heterogeneous integration (HI) play a central role [1, 2] (Fig.1).
Geoffrey Burr, Sidney Tsai, et al.
CICC 2025
Simone Prili, Vara Prasad Jonnalagadda, et al.
MRS Fall Meeting 2024
Olivier Maher, N. Harnack, et al.
DRC 2023
Thomas Lesueur, David Danovitch, et al.
ECTC 2025