Conference paper
Full metal gate with borderless contact for 14 nm and beyond
Soon-Cheon Seo, L.F. Edge, et al.
VLSI Technology 2011
Trapped holes are shown to induce]] slow" interface states by their presence that are distinctly different from other types of interface states. These slow states can be alternately introduced and removed by sequential hole generation and annihilation. Various experiments and techniques are used to rule out explanations involving artifacts due to lateral nonuniformities in the hole trapping. © 1995 American Institute of Physics.
Soon-Cheon Seo, L.F. Edge, et al.
VLSI Technology 2011
D.J. DiMaria, E. Cartier, et al.
Journal of Applied Physics
E. Cartier, J.H. Stathis, et al.
Applied Physics Letters
M.A. Tischler, R.T. Collins, et al.
Applied Physics Letters