Yichen Xu, Baoqi Zhu, et al.
VLSI Technology and Circuits 2026
In this work we demonstrate cryogenic InGaAs/InP HEMTs with highly scaled gate footprints, down to 380 × 40 nm2 for a single gate finger, and investigate the impact of footprint scaling on device performance. The 80% In channel devices show f=622 GHz and f=733 GHz together with a noise indication factor √I/g=0.17 √V·mm/S at 4 K, which is a record-high combination of high-frequency and low-noise performance. The performance is enabled by heterostructure engineering, resulting in ultra-low R=250 Ω·μ m together with a minimum subthreshold swing SS < 10 mV/decade. These results show that cryogenic III-V HEMT technology can provide excellent performance at scaled footprints for readout in future high-density quantum systems.
Yichen Xu, Baoqi Zhu, et al.
VLSI Technology and Circuits 2026
Lin Dong, Steven Hung, et al.
VLSI Technology 2021
Subhajit Ray, David Frank, et al.
VLSI Technology and Circuits 2025
Akihiro Horibe, Yoichi Taira, et al.
IEDM 2025