Process/physics-based threshold voltage model for nano-scaled double-gate devices
- Keunwoo Kim
- Jerry G. Fossum
- et al.
- 2004
- International Journal of Electronics
Paper
Publications
136 results for C.T. Chuang
Performance assessment of scaled strained-Si channel-on-insulator (SSOI) CMOS
- Keunwoo Kim
- Ching-Te Chuang
- et al.
- 2004
- Solid-State Electronics
PaperScaling planar silicon devices
- Ching-Te Chuang
- Kerry Bernstein
- et al.
- 2004
- IEEE Circuits and Devices Magazine
PaperTurning silicon on its edge
- Edward J. Nowak
- Ingo Aller
- et al.
- 2004
- IEEE Circuits and Devices Magazine
PaperPower analysis of strained-Si devices/circuits
- Keunwoo Kim
- Rajiv V. Joshi
- et al.
- 2004
- Solid-State Electronics
PaperRestoration of Controllable Hysteresis in Partially Depleted SOI CMOS Schmitt Trigger Circuits
- Jente B. Kuang
- Ching-Te Chuang
- 2004
- IEEE TCAS-II
PaperPD/SOI SRAM performance in presence of gate-to-body tunneling current
- Rajiv V. Joshi
- Ching-Te Chuang
- et al.
- 2003
- IEEE Transactions on VLSI Systems
PaperAnalysis and modeling methodology of strained-Si channel-on-insulator (SSOI) MOSFETs
- Keunwoo Kim
- Ching-Te Chuang
- et al.
- 2003
- VLSI-TSA 2003
Conference paperHysteresis effect in floating-body partially depleted SOI CMOS domino circuits
- Ruchir Puri
- Ching-Te Chuang
- 2003
- International Journal of Electronics
PaperA New Dynamic Beta-Ratio Circuit Technique for Strained-Si Technology
- Rajiv V. Joshi
- Keunwoo Kim
- et al.
- 2003
- IEEE International SOI Conference 2003
Conference paper