High frequency input isolation circuit for asynchronous CMOS macros in PD/SOI technology
- R.V. Joshi
- W. Hwang
- et al.
- 2000
- IEEE International SOI Conference 2000
Conference paper
Publications
136 results for C.T. Chuang
`Cool low power' 1 GHz multi-port register file and dynamic latch in 1.8 V, 0.25 μm SOI and bulk technology
- R.V. Joshi
- W. Hwang
- et al.
- 2000
- ISLPED 2000
Conference paperHysteresis Effect in Pass-Transistor-Based, Partially Depleted SOI CMOS Circuits
- Ruchir Puri
- Ching-Te Chuang
- 2000
- IEEE Journal of Solid-State Circuits
PaperSOI digital circuits: design issues
- R. Puri
- C.T. Chuang
- 2000
- VLSID 2000
Conference paperFrequency dependent behavior of a high performance dynamic register file in 1.8 V, 0.25 μm SOI technology
- R.V. Joshi
- W. Hwang
- et al.
- 1999
- IEEE International SOI Conference 1999
Conference paperA dynamic body discharge technique for SOI circuit applications
- J.B. Kuang
- M.J. Saccamango
- et al.
- 1999
- IEEE International SOI Conference 1999
Conference paperHysteresis effect in floating-body Partially-Depleted SOI CMOS domino circuits
- R. Puri
- C.T. Chuang
- 1999
- ISLPED 1999
PaperSOI digital CMOS VLSI - a design perspective
- C.T. Chuang
- R. Puri
- 1999
- DAC 1999
Conference paperImplementation of a high speed multiport register file in a 1.8V, 0.25 μm CMOS bulk and SOI technology
- R.V. Joshi
- W. Hwang
- et al.
- 1999
- International Symposium on VLSI Technology, Systems, and Applications, Proceedings
PaperDual-mode parasitic bipolar effect in dynamic CVSL XOR circuit with floating-body partially depleted SOI devices
- C.T. Chuang
- P.F. Lu
- et al.
- 1999
- International Journal of Electronics
Paper