Stress proximity technique for performance improvement with dual stress liner at 45nm technology and beyond
- X. Chen
- S. Fang
- et al.
- 2006
- VLSI Technology 2006
Conference paper
Publications
12 results for Phung T. Nguyen
High performance CMOS bulk technology using direct silicon bond (DSB) mixed crystal orientation substrates
- Chun-Yung Sung
- Haizhou Yin
- et al.
- 2005
- IEDM 2005
Conference paperInteraction of middle-of-line (MOL) temperature and mechanical stress on 90nm hi-speed device performance and reliability
- K.Y. Lim
- V. Chan
- et al.
- 2005
- ESSDERC 2005
Conference paper65nm CMOS technology for low power applications
- A. Steegen
- R. Mo
- et al.
- 2005
- IEDM 2005
Conference paperAdvanced gate stacks with fully silicided (FUSI) gates and high-κ dielectrics: Enhanced performance at reduced gate leakage
- E. Gusev
- C. Cabral Jr.
- et al.
- 2004
- IEDM 2004
Conference paperHigh performance and low power transistors integrated in 65nm bulk CMOS technology
- Z. Luo
- A. Steegen
- et al.
- 2004
- IEDM 2004
Conference paperThermally robust dual-work function ALD-MN x MOSFETs using conventional CMOS process flow
- D.-G. Park
- Z. Luo
- et al.
- 2004
- VLSI Technology 2004
Conference paperDual work function metal gate CMOS using CVD metal electrodes
- V. Narayanan
- A.C. Callegari
- et al.
- 2004
- VLSI Technology 2004
Conference paperScalability and biasing strategy for CMOS with active well bias
- S. Huang
- C. Wann
- et al.
- 2001
- VLSI Technology 2001
Conference paperLow temperature Rdb measurements and simulations for Si npn transistors
- P.T. Nguyen
- S.S. Yao
- et al.
- 1993
- Solid State Electronics
Paper