SMT and enhanced SPT with Recessed SD to improve CMOS Device Performance
- S. Fang
- S.S. Tan
- et al.
- 2008
- ICSICT 2008
Conference paper
Publications
18 results for Z. Luo
Channel Strain Characterization in Embedded SiGe by Nano-beam Diffraction
- J. Li
- A. Lamberti
- et al.
- 2008
- ECS Meeting 2008
Conference paperEffect of end-of-range defects on device leakage in direct silicon bonded (DSB) technology
- Haizhou Yin
- M. Hamaguchi
- et al.
- 2008
- VLSI-TSA 2008
Conference paperScalability of Direct Silicon Bonded (DSB) technology for 32nm node and beyond
- Haizhou Yin
- C.Y. Sung
- et al.
- 2007
- VLSI Technology 2007
Conference paper(110) Channel, SiON gate-dielectric PMOS with record high Ion=1 mA/μm through channel stress and source drain external resistance (R ext) engineering
- B. Yang
- A. Waite
- et al.
- 2007
- IEDM 2007
Conference paperHigh performance transistors featured in an aggressively scaled 45nm bulk CMOS technology
- Z. Luo
- N. Rovedo
- et al.
- 2007
- VLSI Technology 2007
Conference paperStrained Si channel MOSFETs with embedded silicon carbon formed by solid phase epitaxy
- Yaocheng Liu
- Oleg Gluschenkov
- et al.
- 2007
- VLSI Technology 2007
Conference paperDirect silicon bonded (DSB) substrate solid phase epitaxy (SPE) integration scheme study for high performance bulk CMOS
- Haizhou Yin
- C.Y. Sung
- et al.
- 2006
- IEDM 2006
Conference paperStress proximity technique for performance improvement with dual stress liner at 45nm technology and beyond
- X. Chen
- S. Fang
- et al.
- 2006
- VLSI Technology 2006
Conference paperA 45nm low cost low power platform by using integrated dual-stress-liner technology
- J. Yuan
- S.S. Tan
- et al.
- 2006
- VLSI Technology 2006
Conference paper