Understanding and Minimizing Ground Bounce During Mode Transition of Power Gating Structures
- Suhwan Kim
- Stephen V. Kosonocky
- et al.
- 2003
- ISLPED 2003
Conference paper
Publications
31 results for Stephen Kosonocky
Application of an SOI 0.12-μm CMOS technology to SoCs with low-power and high-frequency circuits
- Jean-Olivier Plouchart
- Noah Zamdmer
- et al.
- 2003
- IBM J. Res. Dev
PaperLow-power circuits and technology for wireless digital systems
- Stephen V. Kosonocky
- Azeez J. Bhavnagarwala
- et al.
- 2003
- IBM J. Res. Dev
ReviewLong-term power minimization of dual-νΤ CMOS circuits
- Suhwan Kim
- Youngsoo Shin
- et al.
- 2002
- ASIC/SOC 2002
Conference paperLow power integrated scan-retention mechanism
- Victor Zyuban
- Stephen V. Kosonocky
- 2002
- LPED 2002
Conference paperSupply voltage strategies for minimizing the power of CMOS processors
- Jin Cai
- Yuan Taur
- et al.
- 2002
- VLSI Technology 2002
Conference paperInterconnect-centric array architectures for minimum SRAM access time
- A.J. Bhavnagarwala
- S.V. Kosonocky
- et al.
- 2001
- ICCD 2001
Conference paperMixed multi-threshold differential cascode voltage switch (MT-DCVS) circuit styles and strategies for low power VLSI design
- W. Chen
- W. Hwang
- et al.
- 2001
- ISLPED 2001
Conference paperEnhanced multi-threshold (MTCMOS) circuits using variable well bias
- S.V. Kosonocky
- M.J. Immediato
- et al.
- 2001
- ISLPED 2001
Conference paperDesigning a testable System on a Chip
- S.V. Kosonocky
- A.A. Bright
- et al.
- 1998
- VTS 1998
Conference paper