Vertical-Transport Nanosheet Technology for CMOS Scaling beyond Lateral-Transport Devices
- H. Jagannathan
- B. Anderson
- et al.
- 2021
- IEDM 2021
Conference paper
Publications
20 results for Albert Young
Challenges and Opportunities for Stacked Transistor: DTCO and Device
- J. Wang
- S.D. Suk
- et al.
- 2021
- VLSI Technology 2021
Conference paperSelf-Allancd Gate Contact (SAGC) for CMOS technology scaling beyond 7nm
- Ruilong Xie
- Chanro Park
- et al.
- 2019
- VLSI Technology 2019
Conference paperRapid and Holistic Technology Evaluation for Exploratory DTCO in beyond 7nm Technologies
- Myung-Hee Na
- Albert Chu
- et al.
- 2018
- SISPAD 2018
Conference paperAccurate performance evaluation for the horizontal nanosheet standard-cell design space beyond 7nm technology
- Yoo-Mi Lee
- Myung-Hee Na
- et al.
- 2017
- IEDM 2017
Conference paperStacked nanosheet gate-all-around transistor to enable scaling beyond FinFET
- N. Loubet
- T.B. Hook
- et al.
- 2017
- VLSI Technology 2017
Conference paperCharacterization of TSV-induced loss and substrate noise coupling in advanced three-dimensional CMOS SOI technology
- Xiaoxiong Gu
- Joel A. Silberman
- et al.
- 2013
- IEEE Transactions on CPMT
PaperDesign and modeling methodology of vertical interconnects for 3DI applications
- Rachel Gordin
- David Goren
- et al.
- 2011
- IEEE Transactions on CPMT
PaperElectrical performances and structural designs of copper bonding in wafer-level three-dimensional integration
- K.N. Chen
- A. Young
- et al.
- 2011
- Journal of Nanoscience and Nanotechnology
PaperReliability of a 300-mm-compatible 3DI technology based on hybrid Cu-adhesive wafer bonding
- R.R. Yu
- F. Liu
- et al.
- 2009
- VLSI Technology 2009
Conference paper