Optimization of Cu damascene electrodeposition process in ULSI for yield and reliability improvement
- Ingrid Shao
- T. Cheng
- et al.
- 2013
- ECS Transactions
Conference paper
Publications
45 results for M. Chudzik
22nm High-performance SOI technology featuring dual-embedded stressors, Epi-Plate High-K deep-trench embedded DRAM and self-aligned Via 15LM BEOL
- S. Narasimha
- P. Chang
- et al.
- 2012
- IEDM 2012
Conference paperBias temperature instability in high-κ/metal gate transistors - Gate stack scaling trends
- Siddarth Krishnan
- Vijay Narayanan
- et al.
- 2012
- IRPS 2012
Conference paperA novel low resistance gate fill for extreme gate length scaling at 20nm and beyond for gate-last high-k/metal gate CMOS technology
- U. Kwon
- K. Wong
- et al.
- 2012
- VLSI Technology 2012
Conference paperLow resistivity tungsten for 32 nm node MOL contacts and beyond
- Filippos Papadatos
- Keith Wong
- et al.
- 2012
- Microelectronic Engineering
PaperA manufacturable dual channel (Si and SiGe) high-k metal gate CMOS technology with multiple oxides for high performance and low power applications
- S. Krishnan
- U. Kwon
- et al.
- 2011
- IEDM 2011
Conference paperThe materials and integration challenge in implementing & scaling high-k/metal gate transistors for high performance CMOS
- Michael Chudzik
- 2011
- ADMETA 2011
Conference paperNew layout dependency in high-k/metal gate MOSFETs
- M. Hamaguchi
- Deleep R. Nair
- et al.
- 2011
- IEDM 2011
Conference paperCharacterization of novel TiN/HfO2 metal insulator semiconductor stack for 32nm eDRAM
- Puneet Goyal
- Sneha Gupta
- et al.
- 2010
- IEEE International SOI Conference 2010
Conference paperComparative study of CVD TiN vs. ALD TiN for contact metallization in 32nm node and beyond
- Valli Arunachalam
- Filippos Papadatos
- et al.
- 2010
- ADMETA 2010
Conference paper