NanoStack Transistor Architecture for CMOS 7A Node and Beyond
- S. Reboh
- C. Zhang
- et al.
- 2025
- VLSI Technology and Circuits 2025
Conference paper
Publications
27 results for M. Sankarapandian
Reliable Cu Pillar Undercut Control Using the Endpoint Detection System
- Zachary Gardner
- Soon-Cheon Seo
- et al.
- 2024
- ASMC 2024
Conference paperAn Evaluation of Bath Life Effects on Photoresist Removal for Wafer Level Packaging
- Joel A. Bahena
- Phillip Tyler
- et al.
- 2023
- Advancing Microelectronics
Conference paperManufacturing Yield Improvement for Advanced CMOS Technology Middle-of-Line Interconnect with Cobalt Metallization : YE: YieldEnhancement/Learning
- Susan Fan
- P. Jamison
- et al.
- 2023
- ASMC 2023
Conference paperVertical-Transport Nanosheet Technology for CMOS Scaling beyond Lateral-Transport Devices
- H. Jagannathan
- B. Anderson
- et al.
- 2021
- IEDM 2021
Conference paperResistive Memory Process Optimization for High Resistance Switching Toward Scalable Analog Compute Technology for Deep Learning
- Youngseok Kim
- Soon-Cheon Seo
- et al.
- 2021
- IEEE Electron Device Letters
PaperParasitic Resistance Reduction for Aggressively Scaled Stacked Nanosheet Transistors
- Su-Chen Fan
- Ruilong Xie
- et al.
- 2020
- IITC 2020
Conference paperSelective Enablement of Dual Dipoles for near Bandedge Multi-Vt Solution in High Performance FinFET and Nanosheet Technologies
- Ruqiang Bao
- K. Watanabe
- et al.
- 2020
- VLSI Technology 2020
Conference paperMultiple-Vt Solutions in Nanosheet Technology for High Performance and Low Power Applications
- Ruqiang Bao
- Reinaldo A. Vega
- et al.
- 2019
- IEDM 2019
Conference paperFull Bottom Dielectric Isolation to Enable Stacked Nanosheet Transistor for Low Power and High Performance Applications
- J. Zhang
- S. Pancharatnam
- et al.
- 2019
- IEDM 2019
Conference paper