Publications

9 results for Eric Miller

Scaling Single Expose EUV Gate LER Through Source-Resist-Mask Co-optimization
- - Gopal Kenath
  - Martin Burkhardt
  - et al.
- 2026
- SPIE Advanced Lithography + Patterning 2026
Conference paper
Optimization of 3nm High Performance Nanosheet Technology for 77 K Operation
- - Julien Frougier
  - Ruqiang Bao
  - et al.
- 2025
- GOMACTech 2025
Conference paper
Advanced Multi-Vt Enabled by Selective Layer Reductions for 2nm Nanosheet Technology and Beyond
- - Ruqiang Bao
  - Yusuke Oniki
  - et al.
- 2024
- IEDM 2024
Conference paper
Monolithic Stacked FET with Stepped Channels for Future Logic Technologies
- - Chen Zhang
  - Seungmin Song
  - et al.
- 2024
- IEDM 2024
Conference paper
EUV patterned gate variation reduction in next generation transistor architectures
- - Gopal Kenath
  - Martin Burkhardt
  - et al.
- 2024
- SPIE Advanced Lithography + Patterning 2024
Conference paper
Scaling opportunities for Gate-All-Around and beyond: A patterning perspective
- - Indira Seshadri
  - Eric Miller
  - et al.
- 2023
- IEDM 2023
Invited talk
Hardware Based Performance Assessment of Vertical-Transport Nanosheet Technology
- - Gen Tsutsui
  - Seunghyun Song
  - et al.
- 2022
- IEDM 2022
Invited talk
Etch and Patterning Development for 2nm Node Nanosheet Devices
- - Eric Miller
  - Indira Seshadri
  - et al.
- 2022
- SPIE Advanced Lithography 2022
Invited talk
Measuring Local CD Uniformity in EUV vias with scatterometry and machine learning
- - Dexin Kong
  - Daniel Schmidt
  - et al.
- 2020
- SPIE Advanced Lithography 2020
Conference paper