Scaling Single Expose EUV Gate LER Through Source-Resist-Mask Co-optimization

A key challenge in gate patterning in next generation technology nodes is the implementation of single expose EUV lithography and the mitigation of EUV stochastic effects on gate LWR and LCDU. Here, we demonstrate significant progress towards overcoming this challenge by implementing a source-resist-mask co-optimization methodology. Specifically, through the introduction of 3 beam illumination, next generation resists and masks, we show significant reduction in the low frequency and overall roughness at < 50 nm gate pitches. Finally, we assess the impact on process window and throughput, and the implementation cost of these solutions in 2nm Logic and Beyond.