Rapid and Holistic Technology Evaluation for Exploratory DTCO in beyond 7nm Technologies
- Myung-Hee Na
- Albert Chu
- et al.
- 2018
- SISPAD 2018
Conference paper
Publications
10 results for Yoo-Mi Lee
Accurate performance evaluation for the horizontal nanosheet standard-cell design space beyond 7nm technology
- Yoo-Mi Lee
- Myung-Hee Na
- et al.
- 2017
- IEDM 2017
Conference paperA manufacturable dual channel (Si and SiGe) high-k metal gate CMOS technology with multiple oxides for high performance and low power applications
- S. Krishnan
- U. Kwon
- et al.
- 2011
- IEDM 2011
Conference paperPerformance elements for 28nm gate length bulk devices with gate first high-k metal gate
- Jun Yuan
- C. Gruensfelder
- et al.
- 2010
- ICSICT 2010
Conference paperHigh-κ/metal gate low power bulk technology - Performance evaluation of standard CMOS logic circuits, microprocessor critical path replicas, and SRAM for 45nm and beyond
- D.-G. Park
- K. Stein
- et al.
- 2009
- VLSI-TSA 2009
Conference paper32nm general purpose bulk CMOS technology for high performance applications at low voltage
- F. Arnaud
- J. Liu
- et al.
- 2008
- IEDM 2008
Conference paperA cost effective 32nm high-K/metal gate CMOS technology for low power applications with single-metal/gate-first process
- X. Chen
- S. Samavedam
- et al.
- 2008
- VLSI Technology 2008
Conference paperAnalysis and modeling of threshold voltage mismatch for CMOS at 65 nm and beyond
- Jeffrey B. Johnson
- Terence B. Hook
- et al.
- 2008
- IEEE Electron Device Letters
PaperModeling MOSFET process variation using PSP
- Josef Watts
- Yoo-Mi Lee
- et al.
- 2007
- NSTI-Nanotech 2007
Conference paperSRAM Cell Design for Stability Methodology
- Clement Wann
- Robert Wong
- et al.
- 2005
- VLSI Technology 2005
Conference paper