Modeling of Effective Thermal Resistance in Sub-14-nm Stacked Nanowire and FinFETs
- Ishita Jain
- Anshul Gupta
- et al.
- 2018
- IEEE T-ED
Paper
Publications
22 results for Abhisek Dixit
Series Resistance Reduction with Linearity Assessment for Vertically Stacked Junctionless Accumulation Mode Nanowire FET
- Anil K. Bansal
- Manoj Kumar
- et al.
- 2018
- IEEE T-ED
PaperEvaluation of 10-nm Bulk FinFET RF Performance - Conventional Versus NC-FinFET
- R. Singh
- K. Aditya
- et al.
- 2018
- IEEE Electron Device Letters
Paper3-D LER and RDF Matching Performance of Nanowire FETs in Inversion, Accumulation, and Junctionless Modes
- Anil K. Bansal
- Charu Gupta
- et al.
- 2018
- IEEE T-ED
PaperAnalytical Modeling of Parasitic Capacitance in Inserted-Oxide FinFETs
- R. Singh
- Anshul Gupta
- et al.
- 2017
- IEEE T-ED
PaperComparison of heat outflow in dense sub-14nm contemporary NFETs: Bulk/SOI, inserted-oxide FinFET and nanowire FET
- Ishita Jain
- Anshul Gupta
- et al.
- 2016
- ICEE 2016
Conference paper7-nm Nanowire FET process variation modeling using industry standard BSIM-CMG model
- R. Singh
- K. Aditya
- et al.
- 2016
- ICEE 2016
Conference paperSeries resistance reduction in stacked nanowire FETs for 7-nm CMOS technology
- Anil K. Bansal
- Ishita Jain
- et al.
- 2016
- IEEE J-EDS
PaperNanowire FET design for 7-nm SOI-CMOS technology
- Ishita Jain
- Anil K. Bansal
- et al.
- 2015
- S3S 2015
Conference paperAb initio study of metal grain orientation-dependent work function and its impact on FinFET variability
- Samarth Agarwal
- Rajan Kumar Pandey
- et al.
- 2013
- IEEE T-ED
Paper