Technology viable DC performance elements for Si/SiGe channel CMOS FinFTT
- G. Tsutsui
- Ruqiang Bao
- et al.
- 2016
- IEDM 2016
Conference paper
Publications
12 results for Rajasekhar Venigalla
FINFET technology featuring high mobility SiGe channel for 10nm and beyond
- Dechao Guo
- G. Karve
- et al.
- 2016
- VLSI Technology 2016
Conference paperSi nanowire CMOS fabricated with minimal deviation from RMG FinFET technology showing record performance
- Isaac Lauer
- Nicolas Loubet
- et al.
- 2015
- VLSI Technology 2015
Conference paperOptimizing stressor film deposition sequence in polish rate order for best planarization
- John H. Zhang
- Changyong Xiao
- et al.
- 2011
- MRS Spring Meeting 2011
Conference paperCharacterization of novel TiN/HfO2 metal insulator semiconductor stack for 32nm eDRAM
- Puneet Goyal
- Sneha Gupta
- et al.
- 2010
- IEEE International SOI Conference 2010
Conference paperGate length and performance scaling of undoped-body extremely thin SOI MOSFETs
- Amlan Majumdar
- Xinlin Wang
- et al.
- 2009
- IEEE Electron Device Letters
PaperDeveloping contact oxide CUP process for 32 nm technology nodes
- John H. Zhang
- Rajasekhar Venigalla
- et al.
- 2008
- VMIC 2008
Conference paperHigh-performance undoped-body 8-nm-thin SOI field-effect transistors
- Amlan Majumdar
- Zhibin Ren
- et al.
- 2008
- IEEE Electron Device Letters
PaperEffect of tensile uniaxial stress on the electron transport properties of deeply scaled FD-SOI n-type MOSFETs
- H. Nayfeh
- D. Singh
- et al.
- 2006
- IEEE Electron Device Letters
PaperEffect of contact liner stress in high-performance FDSOI devices with ultra-thin silicon channels and 30 nm gate lengths
- D. Singh
- J. Hergenrother
- et al.
- 2005
- IEEE International SOI Conference 2005
Conference paper