NanoStack Transistor Architecture for CMOS 7A Node and Beyond
- S. Reboh
- C. Zhang
- et al.
- 2025
- VLSI Technology and Circuits 2025
Conference paper
Publications
16 results for Jing Wang
Vertical-Transport Nanosheet Technology for CMOS Scaling beyond Lateral-Transport Devices
- H. Jagannathan
- B. Anderson
- et al.
- 2021
- IEDM 2021
Conference paperChallenges and Opportunities for Stacked Transistor: DTCO and Device
- J. Wang
- S.D. Suk
- et al.
- 2021
- VLSI Technology 2021
Conference paperFINFET technology featuring high mobility SiGe channel for 10nm and beyond
- Dechao Guo
- G. Karve
- et al.
- 2016
- VLSI Technology 2016
Conference paperGate stack resistance and limits to CMOS logic performance
- Richard A. Wachnik
- Sungjae Lee
- et al.
- 2014
- IEEE TCAS-I
PaperA fully automated method to create Monte-Carlo MOSFET model libraries for statistical circuit simulations
- Jing Wang
- Henry Trombley
- et al.
- 2012
- NSTI-Nanotech 2012
Conference paperSub-25nm FinFET with advanced fin formation and short channel effect engineering
- Tenko Yamashita
- Veeraraghvan S. Basker
- et al.
- 2011
- VLSI Technology 2011
Conference paperOpportunities and challenges of FinFET as a device structure candidate for 14nm node CMOS technology
- Tenko Yamashita
- Veeraraghvan S. Basker
- et al.
- 2011
- CSTIC 2011
Conference paperA 0.063 μm2 FinFET SRAM cell demonstration with conventional lithography using a novel integration scheme with aggressively scaled fin and gate pitch
- Veeraraghvan S. Basker
- Theodorus E. Standaert
- et al.
- 2010
- VLSI Technology 2010
Conference paperRF modeling of 45nm low-power CMOS technology
- Jing Wang
- Hongmei Li
- et al.
- 2009
- NSTI-Nanotech 2009
Conference paper