The NorthPole Validator: A Cycle-Accurate Simulator for HW/SW Codesign of a Prescheduled Neural Inference Accelerator
- Alexander Andreopoulos
- Michael V. Debole
- et al.
- 2025
- HPEC 2025
Conference paper
Publications
86 results for William P. Risk
11.4 IBM NorthPole: An Architecture for Neural Network Inference with a 12nm Chip
- 2024
- ISSCC 2024
Conference paperNeural inference at the frontier of energy, space, and time
- 2023
- Science
PaperIBM NorthPole Neural Inference Machine
- 2023
- HCS 2023
Conference paperTrueNorth Ecosystem for Brain-Inspired Computing: Scalable Systems, Software, and Applications
- Jun Sawada
- Filipp Akopyan
- et al.
- 2016
- SC 2016
Conference paperTrueNorth: Design and Tool Flow of a 65 mW 1 Million Neuron Programmable Neurosynaptic Chip
- Filipp Akopyan
- Jun Sawada
- et al.
- 2015
- IEEE TCADIS
PaperVisual saliency on networks of neurosynaptic cores
- Alexander Andreopoulos
- Brian Taba
- et al.
- 2015
- IBM J. Res. Dev
PaperA million spiking-neuron integrated circuit with a scalable communication network and interface
- Paul A. Merolla
- John V. Arthur
- et al.
- 2014
- Science
PaperReal-Time Scalable Cortical Computing at 46 Giga-Synaptic OPS/Watt with ∼100× Speedup in Time-to-Solution and ∼100,000× Reduction in Energy-to-Solution
- Andrew S. Cassidy
- Rodrigo Alvarez-Icaza
- et al.
- 2014
- SC 2014
Conference paperCognitive computing building block: A versatile and efficient digital neuron model for neurosynaptic cores
- Andrew S. Cassidy
- Paul Merolla
- et al.
- 2013
- IJCNN 2013
Conference paper