SRAM and Mixed-Signal Logic With Noise Immunity in 3-nm Nano-Sheet Technology
- Rajiv V. Joshi
- J. Frougier
- et al.
- 2025
- IEEE Open Journal of the Solid State Circuits Society
Paper
Publications
15 results for Carl Radens
High Performance Nanosheet Technology Optimized for 77 K
- R. Bao
- L. Qin
- et al.
- 2023
- IEDM 2023
Conference paperA universal hardware-driven PVT and layout-aware predictive failure analytics for SRAM
- Rajiv V. Joshi
- Sudesh Saroop
- et al.
- 2016
- IEEE Transactions on VLSI Systems
PaperSuper fast physics-based methodology for accurate memory yield prediction
- Rajiv V. Joshi
- Keunwoo Kim
- et al.
- 2015
- IEEE Transactions on VLSI Systems
PaperHigh performance 14nm SOI FinFET CMOS technology with 0.0174μm2 embedded DRAM and 15 levels of Cu metallization
- C.-H.C-H. Lin
- Brian Greene
- et al.
- 2014
- IEDM 2014
Conference paperEmbedded memory considerations in SOI
- G. Wang
- Carl Radens
- et al.
- 2010
- IEEE International SOI Conference 2010
Conference paperA 45nm low power bulk technology featuring carbon co-implantation and laser anneal on 45°-rotated substrate
- J. Yuan
- V. Chan
- et al.
- 2008
- ICSICT 2008
Conference paperA sub-600-mV, fluctuation tolerant 65-nm CMOS SRAM array with dynamic cell biasing
- Azeez J. Bhavnagarwala
- Stephen Kosonocky
- et al.
- 2008
- IEEE Journal of Solid-State Circuits
PaperCharacterization of Across-device Linewidth Variation (ADLV) for 65 nm logic SRAM using CDSEM and linewidth roughness algorithms
- W. Chu
- C. Radens
- et al.
- 2006
- SPIE Advanced Lithography 2006
Conference paperHigh performance 65 nm SOI technology with dual stress liner and low capacitance SRAM cell
- E. Leobandung
- H. Nayakama
- et al.
- 2005
- VLSI Technology 2005
Conference paper