A DPLL-based per core variable frequency clock generator for an eight-core POWER7™ microprocessor
- Jose Tierno
- Alexander Rylyakov
- et al.
- 2010
- VLSI Circuits 2010
Conference paper
Publications
45 results for Jose A. Tierno
An adaptively pipelined mixed synchronous-asynchronous digital FIR filter chip operating at 1.3 gigahertz
- Montek Singh
- Jose A. Tierno
- et al.
- 2010
- IEEE Transactions on VLSI Systems
PaperBang-bang digital PLLS at 11 and 20GHz with sub-200fs integrated jitter for high-speed serial communication applications
- A. Rylyakov
- J. Tierno
- et al.
- 2009
- ISSCC 2009
Conference paperA wide tuning range (1 GHz-to-15 GHz) fractional-N all-digital PLL in 45nm SOI
- Alexander Rylyakov
- Jose Tierno
- et al.
- 2008
- CICC 2008
Conference paperA modular all-digital PLL architecture enabling both 1-to-2GHz and 24-to-32GHz operation in 65NM CMOS
- A. Rylyakov
- J. Tierno
- et al.
- 2008
- ISSCC 2008
Conference paperA Wide Power Supply Range, Wide Tuning Range, All Static CMOS All Digital PLL in 65 nm SOI
- José A. Tierno
- Alexander V. Rylyakov
- et al.
- 2008
- IEEE Journal of Solid-State Circuits
PaperA wide power-supply range (0.5V-to-1.3V) wide tuning range (500 MHz-to-8 GHz) all-static CMOS AD PLL in 65nm SOI
- A. Rylyakov
- J. Tierno
- et al.
- 2007
- ISSCC 2007
Conference paperPerformance of simulated annealing algorithm in equalized multimode fiber links with linear equalizers
- Petar K. Pepeljugoski
- José A. Tierno
- et al.
- 2006
- Journal of Lightwave Technology
PaperCharacterization of equalized 10-Gb/s multimode fibre LAN links using transverse 7-tap analog FIR filter in 0.13-μm CMOS
- Aleksandar Risteski
- Scott Reynolds
- et al.
- 2005
- ECOC 2005
Conference paperDMD characterization of legacy multimode fibers at 1300nm for link equalization purposes
- Petar Pepeljugoski
- Aleksandar Risteski
- et al.
- 2004
- LEOS 2004
Conference paper