A 1.4 pJ/bit, Power-Scalable 16×12 Gb/s Source-Synchronous I/O With DFE Receiver in 32 nm SOI CMOS Technology
- Timothy O. Dickson
- Yong Liu
- et al.
- 2015
- IEEE JSSC
Paper
Publications
45 results for Jose A. Tierno
A 1.4-pJ/b, power-scalable 16×12-Gb/s source-synchronous I/O with DFE receiver in 32nm SOI CMOS technology
- Timothy O. Dickson
- Yong Liu
- et al.
- 2014
- CICC 2014
Conference paperIndirect performance sensing for on-chip self-healing of analog and RF circuits
- Shupeng Sun
- Fa Wang
- et al.
- 2014
- IEEE TCAS-I
PaperA 28 GHz hybrid PLL in 32 nm SOI CMOS
- Mark Ferriss
- Alexander Rylyakov
- et al.
- 2014
- IEEE JSSC
PaperIndirect performance sensing for on-chip analog self-healing via Bayesian model fusion
- S. Sun
- F. Wang
- et al.
- 2013
- CICC 2013
Conference paperA 28GHz hybrid PLL in 32nm SOI CMOS
- Mark Ferriss
- Alexander Rylyakov
- et al.
- 2013
- VLSI Circuits 2013
Conference paperA linearized, low-phase-noise VCO-based 25-GHz PLL with autonomic biasing
- Bodhisatwa Sadhu
- Mark A. Ferriss
- et al.
- 2013
- IEEE JSSC
PaperA 0.1pJ/b 5-to-10Gb/s charge-recycling stacked low-power I/O for on-chip signaling in 45nm CMOS SOI
- Yong Liu
- Ping-Hsuan Hsieh
- et al.
- 2013
- ISSCC 2013
Conference paperAn integral path self-calibration scheme for a dual-loop PLL
- Mark Ferriss
- Jean-Olivier Plouchart
- et al.
- 2013
- IEEE JSSC
PaperA 23.5 GHz PLL with an adaptively biased VCO in 32 nm SOI-CMOS
- Jean-Olivier Plouchart
- Mark A. Ferriss
- et al.
- 2013
- IEEE TCAS-I
Paper