IBM z13 circuit design and methodology
- J. Warnock
- Christopher Berry
- et al.
- 2015
- IBM J. Res. Dev
Paper
Publications
20 results for D.W. Plass
4.1 22nm Next-generation IBM System z microprocessor
- J. Warnock
- Brian Curran
- et al.
- 2015
- ISSCC 2015
Conference paperIBM POWER8 circuit design and energy optimization
- Victor Zyuban
- Joshua Friedrich
- et al.
- 2015
- IBM J. Res. Dev
PaperThe 12-core POWER8™ processor with 7.6 Tb/s IO bandwidth, integrated voltage regulation, and resonant clocking
- Eric J. Fluhr
- Steve Baumgartner
- et al.
- 2015
- IEEE JSSC
PaperPOWER8TM: A 12-core server-class processor in 22nm SOI with 7.6Tb/s off-chip bandwidth
- Eric J. Fluhr
- Joshua Friedrich
- et al.
- 2014
- ISSCC 2014
Conference paperCircuit and physical design of the zenterprise™ ec12 microprocessor chips and multi-chip module
- James Warnock
- Yuen Chan
- et al.
- 2014
- IEEE Journal of Solid-State Circuits
Paper5.5GHz system z microprocessor and multi-chip module
- James Warnock
- Yuen H Chan
- et al.
- 2013
- ISSCC 2013
Conference paperIsolated Preset Architecture for a 32nm SOI embedded DRAM macro
- John Barth
- Don Plass
- et al.
- 2012
- VLSI Circuits 2012
Conference paperA 5.2GHz microprocessor chip for the IBM zEnterprise™ system
- James Warnock
- Y.-H. Chan
- et al.
- 2011
- ISSCC 2011
Conference paperA 45 nm SOI embedded DRAM macro for the POWER™ processor 32 MByte on-chip L3 cache
- John Barth
- Don Plass
- et al.
- 2011
- IEEE Journal of Solid-State Circuits
Paper