An Analytical Metal Resistance Model and Its Application for Sub-22-nm Metal-Gate CMOS
- X. Miao
- Ruqiang Bao
- et al.
- 2015
- IEEE Electron Device Letters
Paper
Publications
13 results for Keith Wong
Replacement metal gate resistance in FinFET architecture modelling, validation and extendibility
- Ruqiang Bao
- Brian Greene
- et al.
- 2015
- IEDM 2015
Conference paperHigh performance bulk planar 20nm CMOS technology for low power mobile applications
- Huiling Shang
- Sameer Jain
- et al.
- 2012
- VLSI Technology 2012
Conference paperA novel low resistance gate fill for extreme gate length scaling at 20nm and beyond for gate-last high-k/metal gate CMOS technology
- U. Kwon
- K. Wong
- et al.
- 2012
- VLSI Technology 2012
Conference paperLow resistivity tungsten for 32 nm node MOL contacts and beyond
- Filippos Papadatos
- Keith Wong
- et al.
- 2012
- Microelectronic Engineering
PaperGate length scaling and high drive currents enabled for high performance SOI technology using high-κ/metal gate
- K. Henson
- H. Bu
- et al.
- 2008
- IEDM 2008
Conference paperA 300-mm wafer-level three-dimensional integration scheme using tungsten through-silicon via and hybrid cu-adhesive bonding
- F. Liu
- R.R. Yu
- et al.
- 2008
- IEDM 2008
Conference paperNi-Pt silicide formation through Ti mediating layers
- Paul Besser
- Christian Lavoie
- et al.
- 2007
- Microelectronic Engineering
PaperLower resistance scaled metal contacts to silicide for advanced CMOS
- A. Topol
- C. Sheraw
- et al.
- 2006
- VLSI Technology 2006
Conference paperHigh performance FDSOI CMOS technology with metal gate and high-k
- Bruce Doris
- Y.-H. Kim
- et al.
- 2005
- VLSI Technology 2005
Conference paper