Impact of lateral asymmetric channel doping on 45-nm-technology N-Type SOI MOSFETs
- Hasan M. Nayfeh
- Nivo Rovedo
- et al.
- 2009
- IEEE Transactions on Electron Devices
Paper
Publications
50 results for Greg Freeman
Scaling deep trench based eDRAM on SOI to 32nm and beyond
- G. Wang
- D. Anand
- et al.
- 2009
- IEDM 2009
Conference paperAccess transistor design and optimization for 65/45nm high performance SOI eDRAM
- G. Wang
- P. Parries
- et al.
- 2008
- VLSI-TSA 2008
Conference paper(110) Channel, SiON gate-dielectric PMOS with record high Ion=1 mA/μm through channel stress and source drain external resistance (R ext) engineering
- B. Yang
- A. Waite
- et al.
- 2007
- IEDM 2007
Conference paperA simple hardware-based statistical model on 65nm SOI CMOS technology
- Q. Liang
- J.B. Johnson
- et al.
- 2007
- ISDRS 2007
Conference paperSOI CMOS technology with 360GHz fT NFET, 260GHz fT PFET, and record circuit performance for millimeter-wave digital and analog system-on-chip applications
- Sungjae Lee
- Jonghae Kim
- et al.
- 2007
- VLSI Technology 2007
Conference paperManufacturable parasitic-aware circuit-level FETs in 65-nm SOI CMOS technology
- Daeik Kim
- Jonghae Kim
- et al.
- 2007
- IEEE Electron Device Letters
PaperRTA-driven intra-die variations in stage delay, and parametric sensitivities for 65nm technology
- I. Ahsan
- N. Zamdmer
- et al.
- 2006
- VLSI Technology 2006
Conference paperPushing the performance limits of SiGe HBT technology
- Marwan Khater
- Thomas Adam
- et al.
- 2006
- ECS Meeting 2006
Conference paperEffect of collector lateral scaling on performance of high-speed SiGe HBTs with fT>300GHz
- J.-S. Rieh
- M. Khater
- et al.
- 2006
- Electronics Letters
Paper