0.026μm2 high performance Embedded DRAM in 22nm technology for server and SOC applications
- C. Pei
- G. Wang
- et al.
- 2014
- IEDM 2014
Conference paper
Publications
17 results for P. Parries
22nm High-performance SOI technology featuring dual-embedded stressors, Epi-Plate High-K deep-trench embedded DRAM and self-aligned Via 15LM BEOL
- S. Narasimha
- P. Chang
- et al.
- 2012
- IEDM 2012
Conference paperPerformance analysis and modeling of deep trench decoupling capacitor for 32 nm high-performance SOI processors and beyond
- Balaji Jayaraman
- Sneha Gupta
- et al.
- 2012
- ICICDT 2012
Conference paperEmbedded memory considerations in SOI
- G. Wang
- Carl Radens
- et al.
- 2010
- IEEE International SOI Conference 2010
Conference paperCharacterization of novel TiN/HfO2 metal insulator semiconductor stack for 32nm eDRAM
- Puneet Goyal
- Sneha Gupta
- et al.
- 2010
- IEEE International SOI Conference 2010
Conference paperA 0.039um2 high performance eDRAM cell based on 32nm high-K/metal SOI technology
- Nauman Z. Butt
- Kevin McStay
- et al.
- 2010
- IEDM 2010
Conference paperScaling deep trench based eDRAM on SOI to 32nm and beyond
- G. Wang
- D. Anand
- et al.
- 2009
- IEDM 2009
Conference paperA 1 MB cache subsystem prototype with 1.8 ns embedded DRAMs in 45 nm SOI CMOS
- Peter J. Klim
- John Barth
- et al.
- 2009
- IEEE Journal of Solid-State Circuits
PaperA novel, low-cost deep trench decoupling capacitor for high-performance, low-power bulk CMOS applications
- Chengwen Pei
- Roger Booth
- et al.
- 2008
- ICSICT 2008
Conference paperAnalysis of retention time distribution of embedded DRAM - A new mMethod to characterize across-chip threshold voltage variation
- W. Kong
- P. Parries
- et al.
- 2008
- IEEE ITC 2008
Conference paper