High performance 14nm SOI FinFET CMOS technology with 0.0174μm2 embedded DRAM and 15 levels of Cu metallization
- C.-H.C-H. Lin
- Brian Greene
- et al.
- 2014
- IEDM 2014
Conference paper
Publications
18 results for Brian Greene
Replacement metal gate resistance in FinFET architecture modelling, validation and extendibility
- Ruqiang Bao
- Brian Greene
- et al.
- 2015
- IEDM 2015
Conference paperImpact of technology scaling in sub-100 nm nMOSFETs on total-dose radiation response and hot-carrier reliability
- Rajan Arora
- Zachary E. Fleetwood
- et al.
- 2014
- IEEE TNS
PaperExperimental analysis and modeling of self heating effect in dielectric isolated planar and fin devices
- S. Lee
- Richard A. Wachnik
- et al.
- 2013
- VLSI Technology 2013
Conference paperAdvanced modeling and optimization of high performance 32nm HKMG SOI CMOS for RF/analog SoC applications
- Sungjae Lee
- J. Johnson
- et al.
- 2012
- VLSI Technology 2012
Conference paperA manufacturable dual channel (Si and SiGe) high-k metal gate CMOS technology with multiple oxides for high performance and low power applications
- S. Krishnan
- U. Kwon
- et al.
- 2011
- IEDM 2011
Conference paperChip-level power-performance optimization through thermally-driven across-chip variation (ACV) reduction
- X. Yu
- Oleg Gluschenkov
- et al.
- 2011
- IEDM 2011
Conference paperStress liner effects for 32-nm SOI MOSFETs with HKMG
- Ming Cai
- Karthik Ramani
- et al.
- 2010
- IEEE T-ED
PaperOn the systematic analysis of ring-delay performance using statistical behavior model
- Q. Liang
- B. Greene
- et al.
- 2009
- ISDRS 2009
Conference paperHigh performance 32nm SOI CMOS with high-k/metal gate and 0.149μm 2 SRAM and ultra low-k back end with eleven levels of copper
- B. Greene
- Q. Liang
- et al.
- 2009
- VLSI Technology 2009
Conference paper