3D Chip stacking with 50 μm pitch lead-free micro-c4 interconnections
- Joana Maria
- Bing Dang
- et al.
- 2011
- ECTC 2011
Conference paper
Publications
55 results for Paul Andry
Three-dimensional chip stack with integrated decoupling capacitors and thru-si via interconnects
- Bing Dang
- Michael Shapiro
- et al.
- 2010
- IEEE Electron Device Letters
PaperInvestigations of Cu bond structures and demonstration of a wafer-level 3D integration scheme with W TSVs
- K.N. Chen
- Cyril Cabral Jr.
- et al.
- 2010
- VLSI-TSA 2010
Conference paperCMOS compatible thin wafer processing using temporary mechanical wafer, adhesive and laser release of thin chips/wafers for 3D integration
- Bing Dang
- Paul Andry
- et al.
- 2010
- ECTC 2010
Conference paperIMC bonding for 3D interconnection
- Katsuyuki Sakuma
- Kuniaki Sueoka
- et al.
- 2010
- ECTC 2010
Conference paperNovel adhesive development for CMOS-compatible thin wafer handling
- K. Tamura
- K. Nakada
- et al.
- 2010
- ECTC 2010
Conference paperDie-to-wafer 3D integration technology for high yield and throughput
- Katsuyuki Sakuma
- Paul S. Andry
- et al.
- 2008
- MRS Fall Meeting 2008
Conference paperReliable through silicon vias for 3D silicon applications
- M.J. Shapiro
- M. Interrante
- et al.
- 2009
- IITC 2009
Conference paperCharacterization of stacked die using die-to-wafer integration for high yield and throughput
- K. Sakuma
- P. Andry
- et al.
- 2008
- ECTC 2008
Conference paperReliability testing of through-silicon vias for high-current 3D applications
- Steven L. Wright
- Paul S. Andry
- et al.
- 2008
- ECTC 2008
Conference paper